specialreg.h

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00001 /*-
00002  * Copyright (c) 1991 The Regents of the University of California.
00003  * All rights reserved.
00004  *
00005  * Redistribution and use in source and binary forms, with or without
00006  * modification, are permitted provided that the following conditions
00007  * are met:
00008  * 1. Redistributions of source code must retain the above copyright
00009  *    notice, this list of conditions and the following disclaimer.
00010  * 2. Redistributions in binary form must reproduce the above copyright
00011  *    notice, this list of conditions and the following disclaimer in the
00012  *    documentation and/or other materials provided with the distribution.
00013  * 3. All advertising materials mentioning features or use of this software
00014  *    must display the following acknowledgement:
00015  *      This product includes software developed by the University of
00016  *      California, Berkeley and its contributors.
00017  * 4. Neither the name of the University nor the names of its contributors
00018  *    may be used to endorse or promote products derived from this software
00019  *    without specific prior written permission.
00020  *
00021  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
00022  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
00024  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
00025  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00026  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
00027  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
00028  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
00031  * SUCH DAMAGE.
00032  *
00033  *      @(#)specialreg.h        7.1 (Berkeley) 5/9/91
00034  */
00035 
00036 /*
00037  * Bits in 386 special registers:
00038  */
00039 #define CR0_PE  0x00000001      /* Protected mode Enable */
00040 #define CR0_MP  0x00000002      /* "Math" Present (NPX or NPX emulator) */
00041 #define CR0_EM  0x00000004      /* EMulate non-NPX coproc. (trap ESC only) */
00042 #define CR0_TS  0x00000008      /* Task Switched (if MP, trap ESC and WAIT) */
00043 #define CR0_ET  0x00000010      /* Extension Type (387 (if set) vs 287) */
00044 #define CR0_PG  0x80000000      /* PaGing enable */
00045 
00046 /*
00047  * Bits in 486 special registers:
00048  */
00049 #define CR0_NE  0x00000020      /* Numeric Error enable (EX16 vs IRQ13) */
00050 #define CR0_WP  0x00010000      /* Write Protect (honor PG_RW in all modes) */
00051 #define CR0_AM  0x00040000      /* Alignment Mask (set to enable AC flag) */
00052 #define CR0_NW  0x20000000      /* Not Write-through */
00053 #define CR0_CD  0x40000000      /* Cache Disable */
00054 
00055 /*
00056  * Cyrix 486 DLC special registers, accessible as IO ports.
00057  */
00058 #define CCR0    0xc0            /* configuration control register 0 */
00059 #define CCR0_NC0        0x01    /* first 64K of each 1M memory region is non-cacheable */
00060 #define CCR0_NC1        0x02    /* 640K-1M region is non-cacheable */
00061 #define CCR0_A20M       0x04    /* enables A20M# input pin */
00062 #define CCR0_KEN        0x08    /* enables KEN# input pin */
00063 #define CCR0_FLUSH      0x10    /* enables FLUSH# input pin */
00064 #define CCR0_BARB       0x20    /* flushes internal cache when entering hold state */
00065 #define CCR0_CO         0x40    /* cache org: 1=direct mapped, 0=2x set assoc */
00066 #define CCR0_SUSPEND    0x80    /* enables SUSP# and SUSPA# pins */
00067 
00068 #define CCR1    0xc1            /* configuration control register 1 */
00069 #define CCR1_RPL        0x01    /* enables RPLSET and RPLVAL# pins */
00070 /* the remaining 7 bits of this register are reserved */
00071 
00072 /*
00073  * bits in the pentiums %cr4 register:
00074  */
00075 
00076 #define CR4_VME 0x00000001      /* virtual 8086 mode extension enable */
00077 #define CR4_PVI 0x00000002      /* protected mode virtual interrupt enable */
00078 #define CR4_TSD 0x00000004      /* restrict RDTSC instruction to cpl 0 only */
00079 #define CR4_DE  0x00000008      /* debugging extension */
00080 #define CR4_PSE 0x00000010      /* large (4MB) page size enable */
00081 #define CR4_PAE 0x00000020      /* physical address extension enable */
00082 #define CR4_MCE 0x00000040      /* machine check enable */
00083 #define CR4_PGE 0x00000080      /* page global enable */
00084 #define CR4_PCE 0x00000100      /* enable RDPMC instruction for all cpls */
00085 #define CR4_OSFXSR      0x00000200      /* enable fxsave/fxrestor and SSE */
00086 #define CR4_OSXMMEXCPT  0x00000400      /* enable unmasked SSE exceptions */
00087 
00088 /*
00089  * CPUID "features" bits:
00090  */
00091 
00092 #define CPUID_FPU       0x00000001      /* processor has an FPU? */
00093 #define CPUID_VME       0x00000002      /* has virtual mode (%cr4's VME/PVI) */
00094 #define CPUID_DE        0x00000004      /* has debugging extension */
00095 #define CPUID_PSE       0x00000008      /* has page 4MB page size extension */
00096 #define CPUID_TSC       0x00000010      /* has time stamp counter */
00097 #define CPUID_MSR       0x00000020      /* has mode specific registers */
00098 #define CPUID_PAE       0x00000040      /* has phys address extension */
00099 #define CPUID_MCE       0x00000080      /* has machine check exception */
00100 #define CPUID_CX8       0x00000100      /* has CMPXCHG8B instruction */
00101 #define CPUID_APIC      0x00000200      /* has enabled APIC */
00102 #define CPUID_B10       0x00000400      /* reserved, MTRR */
00103 #define CPUID_SEP       0x00000800      /* has SYSENTER/SYSEXIT extension */
00104 #define CPUID_MTRR      0x00001000      /* has memory type range register */
00105 #define CPUID_PGE       0x00002000      /* has page global extension */
00106 #define CPUID_MCA       0x00004000      /* has machine check architecture */
00107 #define CPUID_CMOV      0x00008000      /* has CMOVcc instruction */
00108 #define CPUID_FGPAT     0x00010000      /* Page Attribute Table */
00109 #define CPUID_PSE36     0x00020000      /* 36-bit PSE */
00110 #define CPUID_PN        0x00040000      /* processor serial number */
00111 #define CPUID_CFLUSH    0x00080000      /* CFLUSH insn supported */
00112 #define CPUID_B20       0x00100000      /* reserved */
00113 #define CPUID_DS        0x00200000      /* Debug Store */
00114 #define CPUID_ACPI      0x00400000      /* ACPI performance modulation regs */
00115 #define CPUID_MMX       0x00800000      /* MMX supported */
00116 #define CPUID_FXSR      0x01000000      /* fast FP/MMX save/restore */
00117 #define CPUID_SSE       0x02000000      /* streaming SIMD extensions */
00118 #define CPUID_SSE2      0x04000000      /* streaming SIMD extensions #2 */
00119 #define CPUID_SS        0x08000000      /* self-snoop */
00120 #define CPUID_HTT       0x10000000      /* Hyper-Threading Technology */
00121 #define CPUID_TM        0x20000000      /* thermal monitor (TCC) */
00122 #define CPUID_B30       0x40000000      /* reserved */
00123 #define CPUID_B31       0x80000000      /* reserved */
00124 
00125 #define CPUID_FLAGS1    "\20\1FPU\2VME\3DE\4PSE\5TSC\6MSR\7PAE" \
00126                             "\10MCE\11CX8\12APIC\13B10\14SEP\15MTRR"
00127 #define CPUID_MASK1     0x00001fff
00128 #define CPUID_FLAGS2    "\20\16PGE\17MCA\20CMOV\21FGPAT\22PSE36\23PN\24CFLUSH" \
00129                             "\25B20\26DS\27ACPI\30MMX"
00130 #define CPUID_MASK2     0x00ffe000
00131 #define CPUID_FLAGS3    "\20\31FXSR\32SSE\33SSE2\34SS\35HTT\36TM\37B30\40B31"
00132 #define CPUID_MASK3     0xff000000
00133 
00134 /*
00135  * Model-specific registers for the i386 family
00136  */
00137 #define MSR_P5_MC_ADDR          0x000   /* P5 only */
00138 #define MSR_P5_MC_TYPE          0x001   /* P5 only */
00139 #define MSR_TSC                 0x010
00140 #define MSR_CESR                0x011   /* P5 only (trap on P6) */
00141 #define MSR_CTR0                0x012   /* P5 only (trap on P6) */
00142 #define MSR_CTR1                0x013   /* P5 only (trap on P6) */
00143 #define MSR_APICBASE            0x01b
00144 #define MSR_EBL_CR_POWERON      0x02a
00145 #define MSR_TEST_CTL            0x033
00146 #define MSR_BIOS_UPDT_TRIG      0x079
00147 #define MSR_BBL_CR_D0           0x088   /* PII+ only */
00148 #define MSR_BBL_CR_D1           0x089   /* PII+ only */
00149 #define MSR_BBL_CR_D2           0x08a   /* PII+ only */
00150 #define MSR_BIOS_SIGN           0x08b
00151 #define MSR_PERFCTR0            0x0c1
00152 #define MSR_PERFCTR1            0x0c2
00153 #define MSR_MTRRcap             0x0fe
00154 #define MSR_BBL_CR_ADDR         0x116   /* PII+ only */
00155 #define MSR_BBL_CR_DECC         0x118   /* PII+ only */
00156 #define MSR_BBL_CR_CTL          0x119   /* PII+ only */
00157 #define MSR_BBL_CR_TRIG         0x11a   /* PII+ only */
00158 #define MSR_BBL_CR_BUSY         0x11b   /* PII+ only */
00159 #define MSR_BBL_CR_CTR3         0x11e   /* PII+ only */
00160 #define MSR_MCG_CAP             0x179
00161 #define MSR_MCG_STATUS          0x17a
00162 #define MSR_MCG_CTL             0x17b
00163 #define MSR_EVNTSEL0            0x186
00164 #define MSR_EVNTSEL1            0x187
00165 #define MSR_DEBUGCTLMSR         0x1d9
00166 #define MSR_LASTBRANCHFROMIP    0x1db
00167 #define MSR_LASTBRANCHTOIP      0x1dc
00168 #define MSR_LASTINTFROMIP       0x1dd
00169 #define MSR_LASTINTTOIP         0x1de
00170 #define MSR_ROB_CR_BKUPTMPDR6   0x1e0
00171 #define MSR_MTRRphysBase0       0x200
00172 #define MSR_MTRRphysMask0       0x201
00173 #define MSR_MTRRphysBase1       0x202
00174 #define MSR_MTRRphysMask1       0x203
00175 #define MSR_MTRRphysBase2       0x204
00176 #define MSR_MTRRphysMask2       0x205
00177 #define MSR_MTRRphysBase3       0x206
00178 #define MSR_MTRRphysMask3       0x207
00179 #define MSR_MTRRphysBase4       0x208
00180 #define MSR_MTRRphysMask4       0x209
00181 #define MSR_MTRRphysBase5       0x20a
00182 #define MSR_MTRRphysMask5       0x20b
00183 #define MSR_MTRRphysBase6       0x20c
00184 #define MSR_MTRRphysMask6       0x20d
00185 #define MSR_MTRRphysBase7       0x20e
00186 #define MSR_MTRRphysMask7       0x20f
00187 #define MSR_MTRRfix64K_00000    0x250
00188 #define MSR_MTRRfix16K_80000    0x258
00189 #define MSR_MTRRfix16K_A0000    0x259
00190 #define MSR_MTRRfix4K_C0000     0x268
00191 #define MSR_MTRRfix4K_C8000     0x269
00192 #define MSR_MTRRfix4K_D0000     0x26a
00193 #define MSR_MTRRfix4K_D8000     0x26b
00194 #define MSR_MTRRfix4K_E0000     0x26c
00195 #define MSR_MTRRfix4K_E8000     0x26d
00196 #define MSR_MTRRfix4K_F0000     0x26e
00197 #define MSR_MTRRfix4K_F8000     0x26f
00198 #define MSR_MTRRdefType         0x2ff
00199 #define MSR_MC0_CTL             0x400
00200 #define MSR_MC0_STATUS          0x401
00201 #define MSR_MC0_ADDR            0x402
00202 #define MSR_MC0_MISC            0x403
00203 #define MSR_MC1_CTL             0x404
00204 #define MSR_MC1_STATUS          0x405
00205 #define MSR_MC1_ADDR            0x406
00206 #define MSR_MC1_MISC            0x407
00207 #define MSR_MC2_CTL             0x408
00208 #define MSR_MC2_STATUS          0x409
00209 #define MSR_MC2_ADDR            0x40a
00210 #define MSR_MC2_MISC            0x40b
00211 #define MSR_MC4_CTL             0x40c
00212 #define MSR_MC4_STATUS          0x40d
00213 #define MSR_MC4_ADDR            0x40e
00214 #define MSR_MC4_MISC            0x40f
00215 #define MSR_MC3_CTL             0x410
00216 #define MSR_MC3_STATUS          0x411
00217 #define MSR_MC3_ADDR            0x412
00218 #define MSR_MC3_MISC            0x413
00219 
00220 /*
00221  * AMD K6 MSRs.
00222  */
00223 #define MSR_K6_UWCCR            0xc0000085
00224 
00225 /*
00226  * Constants related to MTRRs
00227  */
00228 #define MTRR_N64K               8       /* numbers of fixed-size entries */
00229 #define MTRR_N16K               16
00230 #define MTRR_N4K                64
00231 
00232 /*
00233  * the following four 3-byte registers control the non-cacheable regions.
00234  * These registers must be written as three separate bytes.
00235  *
00236  * NCRx+0: A31-A24 of starting address
00237  * NCRx+1: A23-A16 of starting address
00238  * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx.
00239  * 
00240  * The non-cacheable region's starting address must be aligned to the
00241  * size indicated by the NCR_SIZE_xx field.
00242  */
00243 #define NCR1    0xc4
00244 #define NCR2    0xc7
00245 #define NCR3    0xca
00246 #define NCR4    0xcd
00247 
00248 #define NCR_SIZE_0K     0
00249 #define NCR_SIZE_4K     1
00250 #define NCR_SIZE_8K     2
00251 #define NCR_SIZE_16K    3
00252 #define NCR_SIZE_32K    4
00253 #define NCR_SIZE_64K    5
00254 #define NCR_SIZE_128K   6
00255 #define NCR_SIZE_256K   7
00256 #define NCR_SIZE_512K   8
00257 #define NCR_SIZE_1M     9
00258 #define NCR_SIZE_2M     10
00259 #define NCR_SIZE_4M     11
00260 #define NCR_SIZE_8M     12
00261 #define NCR_SIZE_16M    13
00262 #define NCR_SIZE_32M    14
00263 #define NCR_SIZE_4G     15
00264 
00265 /*
00266  * Performance monitor events.
00267  *
00268  * Note that 586-class and 686-class CPUs have different performance
00269  * monitors available, and they are accessed differently:
00270  *
00271  *      686-class: `rdpmc' instruction
00272  *      586-class: `rdmsr' instruction, CESR MSR
00273  *
00274  * The descriptions of these events are too lenghy to include here.
00275  * See Appendix A of "Intel Architecture Software Developer's
00276  * Manual, Volume 3: System Programming" for more information.
00277  */
00278 
00279 /*
00280  * 586-class CESR MSR format.  Lower 16 bits is CTR0, upper 16 bits
00281  * is CTR1.
00282  */
00283 
00284 #define PMC5_CESR_EVENT                 0x003f
00285 #define PMC5_CESR_OS                    0x0040
00286 #define PMC5_CESR_USR                   0x0080
00287 #define PMC5_CESR_E                     0x0100
00288 #define PMC5_CESR_P                     0x0200
00289 
00290 /*
00291  * 686-class Event Selector MSR format.
00292  */
00293 
00294 #define PMC6_EVTSEL_EVENT               0x000000ff
00295 #define PMC6_EVTSEL_UNIT                0x0000ff00
00296 #define PMC6_EVTSEL_UNIT_SHIFT          8
00297 #define PMC6_EVTSEL_USR                 (1 << 16)
00298 #define PMC6_EVTSEL_OS                  (1 << 17)
00299 #define PMC6_EVTSEL_E                   (1 << 18)
00300 #define PMC6_EVTSEL_PC                  (1 << 19)
00301 #define PMC6_EVTSEL_INT                 (1 << 20)
00302 #define PMC6_EVTSEL_EN                  (1 << 22)       /* PerfEvtSel0 only */
00303 #define PMC6_EVTSEL_INV                 (1 << 23)
00304 #define PMC6_EVTSEL_COUNTER_MASK        0xff000000
00305 #define PMC6_EVTSEL_COUNTER_MASK_SHIFT  24
00306 
00307 /* Data Cache Unit */
00308 #define PMC6_DATA_MEM_REFS              0x43
00309 #define PMC6_DCU_LINES_IN               0x45
00310 #define PMC6_DCU_M_LINES_IN             0x46
00311 #define PMC6_DCU_M_LINES_OUT            0x47
00312 #define PMC6_DCU_MISS_OUTSTANDING       0x48
00313 
00314 /* Instruction Fetch Unit */
00315 #define PMC6_IFU_IFETCH                 0x80
00316 #define PMC6_IFU_IFETCH_MISS            0x81
00317 #define PMC6_ITLB_MISS                  0x85
00318 #define PMC6_IFU_MEM_STALL              0x86
00319 #define PMC6_ILD_STALL                  0x87
00320 
00321 /* L2 Cache */
00322 #define PMC6_L2_IFETCH                  0x28
00323 #define PMC6_L2_LD                      0x29
00324 #define PMC6_L2_ST                      0x2a
00325 #define PMC6_L2_LINES_IN                0x24
00326 #define PMC6_L2_LINES_OUT               0x26
00327 #define PMC6_L2_M_LINES_INM             0x25
00328 #define PMC6_L2_M_LINES_OUTM            0x27
00329 #define PMC6_L2_RQSTS                   0x2e
00330 #define PMC6_L2_ADS                     0x21
00331 #define PMC6_L2_DBUS_BUSY               0x22
00332 #define PMC6_L2_DBUS_BUSY_RD            0x23
00333 
00334 /* External Bus Logic */
00335 #define PMC6_BUS_DRDY_CLOCKS            0x62
00336 #define PMC6_BUS_LOCK_CLOCKS            0x63
00337 #define PMC6_BUS_REQ_OUTSTANDING        0x60
00338 #define PMC6_BUS_TRAN_BRD               0x65
00339 #define PMC6_BUS_TRAN_RFO               0x66
00340 #define PMC6_BUS_TRANS_WB               0x67
00341 #define PMC6_BUS_TRAN_IFETCH            0x68
00342 #define PMC6_BUS_TRAN_INVAL             0x69
00343 #define PMC6_BUS_TRAN_PWR               0x6a
00344 #define PMC6_BUS_TRANS_P                0x6b
00345 #define PMC6_BUS_TRANS_IO               0x6c
00346 #define PMC6_BUS_TRAN_DEF               0x6d
00347 #define PMC6_BUS_TRAN_BURST             0x6e
00348 #define PMC6_BUS_TRAN_ANY               0x70
00349 #define PMC6_BUS_TRAN_MEM               0x6f
00350 #define PMC6_BUS_DATA_RCV               0x64
00351 #define PMC6_BUS_BNR_DRV                0x61
00352 #define PMC6_BUS_HIT_DRV                0x7a
00353 #define PMC6_BUS_HITM_DRDV              0x7b
00354 #define PMC6_BUS_SNOOP_STALL            0x7e
00355 
00356 /* Floating Point Unit */
00357 #define PMC6_FLOPS                      0xc1
00358 #define PMC6_FP_COMP_OPS_EXE            0x10
00359 #define PMC6_FP_ASSIST                  0x11
00360 #define PMC6_MUL                        0x12
00361 #define PMC6_DIV                        0x12
00362 #define PMC6_CYCLES_DIV_BUSY            0x14
00363 
00364 /* Memory Ordering */
00365 #define PMC6_LD_BLOCKS                  0x03
00366 #define PMC6_SB_DRAINS                  0x04
00367 #define PMC6_MISALIGN_MEM_REF           0x05
00368 #define PMC6_EMON_KNI_PREF_DISPATCHED   0x07    /* P-III only */
00369 #define PMC6_EMON_KNI_PREF_MISS         0x4b    /* P-III only */
00370 
00371 /* Instruction Decoding and Retirement */
00372 #define PMC6_INST_RETIRED               0xc0
00373 #define PMC6_UOPS_RETIRED               0xc2
00374 #define PMC6_INST_DECODED               0xd0
00375 #define PMC6_EMON_KNI_INST_RETIRED      0xd8
00376 #define PMC6_EMON_KNI_COMP_INST_RET     0xd9
00377 
00378 /* Interrupts */
00379 #define PMC6_HW_INT_RX                  0xc8
00380 #define PMC6_CYCLES_INT_MASKED          0xc6
00381 #define PMC6_CYCLES_INT_PENDING_AND_MASKED 0xc7
00382 
00383 /* Branches */
00384 #define PMC6_BR_INST_RETIRED            0xc4
00385 #define PMC6_BR_MISS_PRED_RETIRED       0xc5
00386 #define PMC6_BR_TAKEN_RETIRED           0xc9
00387 #define PMC6_BR_MISS_PRED_TAKEN_RET     0xca
00388 #define PMC6_BR_INST_DECODED            0xe0
00389 #define PMC6_BTB_MISSES                 0xe2
00390 #define PMC6_BR_BOGUS                   0xe4
00391 #define PMC6_BACLEARS                   0xe6
00392 
00393 /* Stalls */
00394 #define PMC6_RESOURCE_STALLS            0xa2
00395 #define PMC6_PARTIAL_RAT_STALLS         0xd2
00396 
00397 /* Segment Register Loads */
00398 #define PMC6_SEGMENT_REG_LOADS          0x06
00399 
00400 /* Clocks */
00401 #define PMC6_CPU_CLK_UNHALTED           0x79
00402 
00403 /* MMX Unit */
00404 #define PMC6_MMX_INSTR_EXEC             0xb0    /* Celeron, P-II, P-IIX only */
00405 #define PMC6_MMX_SAT_INSTR_EXEC         0xb1    /* P-II and P-III only */
00406 #define PMC6_MMX_UOPS_EXEC              0xb2    /* P-II and P-III only */
00407 #define PMC6_MMX_INSTR_TYPE_EXEC        0xb3    /* P-II and P-III only */
00408 #define PMC6_FP_MMX_TRANS               0xcc    /* P-II and P-III only */
00409 #define PMC6_MMX_ASSIST                 0xcd    /* P-II and P-III only */
00410 #define PMC6_MMX_INSTR_RET              0xc3    /* P-II only */
00411 
00412 /* Segment Register Renaming */
00413 #define PMC6_SEG_RENAME_STALLS          0xd4    /* P-II and P-III only */
00414 #define PMC6_SEG_REG_RENAMES            0xd5    /* P-II and P-III only */
00415 #define PMC6_RET_SEG_RENAMES            0xd6    /* P-II and P-III only */

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