idevar.h

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/*
** idesrv.h for  in /root/research/lseosr2/include/lseos
** 
** Copyright (c)2004 Julien Quintard
** Login   <quinta_j@epita.fr>
** 
** Started on  Sat Feb 14 14:57:22 2004 Julien Quintard
** Last update Mon Dec  6 12:23:07 2004 Vianney Rancurel
*/
#ifndef __IDEVAR_H__
#define __IDEVAR_H__      1
#include <libc.h>

#undef DEBUG_IDE

/*
 * ide constants values
 */

#define IDE_DEV1                        0x1
#define IDE_DEV2                        0x2
#define IDE_DEV3                        0x3
#define IDE_DEV4                        0x4

#define ATA_TIMEOUT                     32000

#define ATAPI_MAGIC_LSB                 0x14
#define ATAPI_MAGIC_MSB                 0xeb

#define ATA_SECTOR_SIZE                 0x200
#define ATA_BLOCK_SIZE                  ATA_SECTOR_SIZE

/*
 * ide syscalls
 */

#define SYSIDE_GETDRIVE                 0x1
#define SYSIDE_READ                     0x2
#define SYSIDE_WRITE                    0x3

/*
 * command status codes
 */

#define ATA_CMD_EBSY                    0x1 /* busy bit set           */
#define ATA_CMD_EERR                    0x2 /* error bit set          */
#define ATA_CMD_EDRQ                    0x3 /* drq bit set            */
#define ATA_CMD_ETMODE                  0x4 /* unknown transfer mode  */
#define ATA_CMD_EPMODE                  0x5 /* unknown pio mode       */
#define ATA_CMD_ENSL                    0x6 /* no sector left         */
#define ATA_CMD_EMSL                    0x7 /* more sectors left      */
#define ATA_CMD_EBADREQ                 0x8 /* bad request            */

typedef struct          s_device
{
  u_int8_t              d_unit;
  char                  d_id;
  u_int8_t              d_type;
  u_int8_t              d_removable;
  u_int8_t              d_dma;
  char                  d_model[41];
  u_int32_t             d_sectors;
  u_int32_t             d_dev;
}                       t_device;

typedef struct          s_ata_cmd
{
  u_int32_t             cmd_command;
  u_int32_t             cmd_offset;
  u_int16_t             cmd_count;
  u_int16_t             cmd_cylinder;
  u_int16_t             cmd_head;
  u_int16_t             cmd_sector;
  u_int32_t             cmd_lba;
  void                  *cmd_buffer;
  u_int16_t             cmd_transfered;
}                       t_ata_cmd;

typedef struct          s_ata_chs
{
  u_int16_t             chs_heads;
  u_int16_t             chs_cylinders;
  u_int16_t             chs_spt;
}                       t_ata_chs;

typedef struct          s_ide_drv
{

#define ATA_MASTER                      0x00
#define ATA_SLAVE                       0x01

  u_int8_t              d_unit;

  char                  d_id;

#define ATA_STATE_NP                    0x00
#define ATA_STATE_IDLE                  0x01
#define ATA_STATE_WORK                  0x02

  u_int8_t              d_state;

#define ATA_TYPE_NONE                   0x00
#define ATA_TYPE_UNKNOWN                0x01
#define ATA_TYPE_ATA                    0x02
#define ATA_TYPE_ATAPI                  0x03

  u_int8_t              d_type;

  u_int8_t              d_removable;

#define ATA_MODE_NONE                   0x00
#define ATA_MODE_PIO16                  0x01
#define ATA_MODE_PIO32                  0x02

  u_int8_t              d_mode;

#define ATA_DMA_DISABLE                 0x0
#define ATA_DMA_ENABLE                  0x1

  u_int8_t              d_dma;

#define ATA_TRANS_NONE                  0x00
#define ATA_TRANS_LBA                   0x01
#define ATA_TRANS_RECHS                 0x02
#define ATA_TRANS_LARGE                 0x03
#define ATA_TRANS_UNKNOWN               0x04

  u_int8_t              d_trans;

  u_int16_t             d_blksize;

  u_int8_t              d_dma_queue;
  u_int16_t             d_queue_depth;
  u_int16_t             d_mw_dma_cycle_time;

  int16_t               d_ata_version;
  int16_t               d_pio_mode;
  int16_t               d_ultra_dma_mode;
  int16_t               d_dma_mode;

  t_ata_chs             d_lchs;
  t_ata_chs             d_pchs;

  char                  d_model[41];
  char                  d_serial[21];
  char                  d_firmware[9];

  u_int32_t             d_sectors;

  u_int32_t             d_dev;

  /*
   * to set in each task, cause shared memory
   */

  void                  *d_parent_ctrl;
}                       t_ide_drv;

typedef struct          s_ide_ctrl
{

#define ATA_PRIMARY                     0x01
#define ATA_SECONDARY                   0x02

  u_int8_t              c_unit;

#define ATA_P_IOADDR1                   0x1f0
#define ATA_S_IOADDR1                   0x170

  u_int16_t             c_ioaddr1;

#define ATA_P_IOADDR2                   0x3f0
#define ATA_S_IOADDR2                   0x370

  u_int16_t             c_ioaddr2;

#define ATA_P_IRQ                       0x0e
#define ATA_S_IRQ                       0x0f

  u_int8_t              c_irq;

  t_ide_drv             c_master;
  t_ide_drv             c_slave;
}                       t_ide_ctrl;

typedef struct          s_ide_info
{
  __cpu_simple_lock_t   i_lock;
  pid_t                 i_sys_pid;
  pid_t                 i_pri_pid;
  pid_t                 i_sec_pid;

  u_int8_t              i_hd_cnt;
  u_int8_t              i_cd_cnt;
}                       t_ide_info;

typedef struct          s_ide
{
  t_ide_ctrl            i_primary;
  t_ide_ctrl            i_secondary;

  t_ide_info            i_info;

  /* t_ide_queue        i_queue; */
}                       t_ide;

/*
 * main.c
 */

/* PROTO main.c */
#ifdef KERNEL
/* main.c */
#endif /* KERNEL */
#endif

---