pcireg.h

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/*
** pcireg.h for lseos in /home/anoman/work/lse/lseos/lseos-srv/hw/pci
** 
** Copyright (c)2004 Arthur Kopatsy
** Login   <kopats_a@epita.fr>
** 
** Started on  Mon Nov 29 16:00:54 2004 Arthur Kopatsy
** Last update Mon Nov 29 16:03:04 2004 Arthur Kopatsy
*/

/*
** Some define are borrowed from NetBSD
*/


#ifndef PCIREG_H_
# define PCIREG_H_

#include <libc.h>

typedef u_int32_t pci_reg_t;

/*
** Device identification register; contains a vendor ID and a device ID.
*/

#define PCI_ID_REG                              0x00

typedef u_int16_t pci_vendor_t;
typedef u_int16_t pci_product_t;

#define PCI_VENDOR_SHIFT                        0
#define PCI_VENDOR_MASK                         0xffff
#define PCI_VENDOR(pci_id_reg) \
            (((pci_id_reg) >> PCI_VENDOR_SHIFT) & PCI_VENDOR_MASK)

#define PCI_PRODUCT_SHIFT                       16
#define PCI_PRODUCT_MASK                        0xffff
#define PCI_PRODUCT(pci_id_reg) \
            (((pci_id_reg) >> PCI_PRODUCT_SHIFT) & PCI_PRODUCT_MASK)

/*
 * Command and status register.
 */
#define PCI_COMMAND_STATUS_REG                  0x04

#define PCI_COMMAND_SHIFT                       0
#define PCI_COMMAND_MASK                        0xffff
#define PCI_STATUS_SHIFT                        16
#define PCI_STATUS_MASK                         0xffff

#define PCI_COMMAND_STATUS_CODE(command,status)                 \
        ((((command) & PCI_COMMAND_MASK) >> PCI_COMMAND_SHIFT) |        \
         (((status) & PCI_STATUS_MASK) >> PCI_STATUS_SHIFT))    \

#define PCI_COMMAND_IO_ENABLE                   0x00000001
#define PCI_COMMAND_MEM_ENABLE                  0x00000002
#define PCI_COMMAND_MASTER_ENABLE               0x00000004
#define PCI_COMMAND_SPECIAL_ENABLE              0x00000008
#define PCI_COMMAND_INVALIDATE_ENABLE           0x00000010
#define PCI_COMMAND_PALETTE_ENABLE              0x00000020
#define PCI_COMMAND_PARITY_ENABLE               0x00000040
#define PCI_COMMAND_STEPPING_ENABLE             0x00000080
#define PCI_COMMAND_SERR_ENABLE                 0x00000100
#define PCI_COMMAND_BACKTOBACK_ENABLE           0x00000200

#define PCI_STATUS_CAPLIST_SUPPORT              0x00100000
#define PCI_STATUS_66MHZ_SUPPORT                0x00200000
#define PCI_STATUS_UDF_SUPPORT                  0x00400000
#define PCI_STATUS_BACKTOBACK_SUPPORT           0x00800000
#define PCI_STATUS_PARITY_ERROR                 0x01000000
#define PCI_STATUS_DEVSEL_FAST                  0x00000000
#define PCI_STATUS_DEVSEL_MEDIUM                0x02000000
#define PCI_STATUS_DEVSEL_SLOW                  0x04000000
#define PCI_STATUS_DEVSEL_MASK                  0x06000000
#define PCI_STATUS_TARGET_TARGET_ABORT          0x08000000
#define PCI_STATUS_MASTER_TARGET_ABORT          0x10000000
#define PCI_STATUS_MASTER_ABORT                 0x20000000
#define PCI_STATUS_SPECIAL_ERROR                0x40000000
#define PCI_STATUS_PARITY_DETECT                0x80000000

/*
** PCI Class and Revision Register; defines type and revision of device.
*/
#define PCI_CLASS_REG                           0x08

typedef u_int8_t pci_class_t;
typedef u_int8_t pci_subclass_t;
typedef u_int8_t pci_interface_t;
typedef u_int8_t pci_revision_t;

#define PCI_CLASS_SHIFT                         24
#define PCI_CLASS_MASK                          0xff
#define PCI_CLASS(pci_class_reg) \
            (((pci_class_reg) >> PCI_CLASS_SHIFT) & PCI_CLASS_MASK)

#define PCI_SUBCLASS_SHIFT                      16
#define PCI_SUBCLASS_MASK                       0xff
#define PCI_SUBCLASS(pci_class_reg) \
            (((pci_class_reg) >> PCI_SUBCLASS_SHIFT) & PCI_SUBCLASS_MASK)

#define PCI_INTERFACE_SHIFT                     8
#define PCI_INTERFACE_MASK                      0xff
#define PCI_INTERFACE(pci_class_reg) \
            (((pci_class_reg) >> PCI_INTERFACE_SHIFT) & PCI_INTERFACE_MASK)

#define PCI_REVISION_SHIFT                      0
#define PCI_REVISION_MASK                       0xff
#define PCI_REVISION(pci_class_reg) \
            (((pci_class_reg) >> PCI_REVISION_SHIFT) & PCI_REVISION_MASK)

/* base classes */
#define PCI_CLASS_PREHISTORIC                   0x00
#define PCI_CLASS_MASS_STORAGE                  0x01
#define PCI_CLASS_NETWORK                       0x02
#define PCI_CLASS_DISPLAY                       0x03
#define PCI_CLASS_MULTIMEDIA                    0x04
#define PCI_CLASS_MEMORY                        0x05
#define PCI_CLASS_BRIDGE                        0x06
#define PCI_CLASS_COMMUNICATIONS                0x07
#define PCI_CLASS_SYSTEM                        0x08
#define PCI_CLASS_INPUT                         0x09
#define PCI_CLASS_DOCK                          0x0a
#define PCI_CLASS_PROCESSOR                     0x0b
#define PCI_CLASS_SERIALBUS                     0x0c
#define PCI_CLASS_WIRELESS                      0x0d
#define PCI_CLASS_I2O                           0x0e
#define PCI_CLASS_SATCOM                        0x0f
#define PCI_CLASS_CRYPTO                        0x10
#define PCI_CLASS_DASP                          0x11
#define PCI_CLASS_UNDEFINED                     0xff

/* 0x00 prehistoric subclasses */
#define PCI_SUBCLASS_PREHISTORIC_MISC           0x00
#define PCI_SUBCLASS_PREHISTORIC_VGA            0x01

/* 0x01 mass storage subclasses */
#define PCI_SUBCLASS_MASS_STORAGE_SCSI          0x00
#define PCI_SUBCLASS_MASS_STORAGE_IDE           0x01
#define PCI_SUBCLASS_MASS_STORAGE_FLOPPY        0x02
#define PCI_SUBCLASS_MASS_STORAGE_IPI           0x03
#define PCI_SUBCLASS_MASS_STORAGE_RAID          0x04
#define PCI_SUBCLASS_MASS_STORAGE_ATA           0x05
#define PCI_SUBCLASS_MASS_STORAGE_SATA          0x06
#define PCI_SUBCLASS_MASS_STORAGE_MISC          0x80

/* 0x02 network subclasses */
#define PCI_SUBCLASS_NETWORK_ETHERNET           0x00
#define PCI_SUBCLASS_NETWORK_TOKENRING          0x01
#define PCI_SUBCLASS_NETWORK_FDDI               0x02
#define PCI_SUBCLASS_NETWORK_ATM                0x03
#define PCI_SUBCLASS_NETWORK_ISDN               0x04
#define PCI_SUBCLASS_NETWORK_WORLDFIP           0x05
#define PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP     0x06
#define PCI_SUBCLASS_NETWORK_MISC               0x80

/* 0x03 display subclasses */
#define PCI_SUBCLASS_DISPLAY_VGA                0x00
#define PCI_SUBCLASS_DISPLAY_XGA                0x01
#define PCI_SUBCLASS_DISPLAY_3D                 0x02
#define PCI_SUBCLASS_DISPLAY_MISC               0x80

/* 0x04 multimedia subclasses */
#define PCI_SUBCLASS_MULTIMEDIA_VIDEO           0x00
#define PCI_SUBCLASS_MULTIMEDIA_AUDIO           0x01
#define PCI_SUBCLASS_MULTIMEDIA_TELEPHONY       0x02
#define PCI_SUBCLASS_MULTIMEDIA_MISC            0x80

/* 0x05 memory subclasses */
#define PCI_SUBCLASS_MEMORY_RAM                 0x00
#define PCI_SUBCLASS_MEMORY_FLASH               0x01
#define PCI_SUBCLASS_MEMORY_MISC                0x80

/* 0x06 bridge subclasses */
#define PCI_SUBCLASS_BRIDGE_HOST                0x00
#define PCI_SUBCLASS_BRIDGE_ISA                 0x01
#define PCI_SUBCLASS_BRIDGE_EISA                0x02
#define PCI_SUBCLASS_BRIDGE_MC                  0x03    /* XXX _MCA? */
#define PCI_SUBCLASS_BRIDGE_PCI                 0x04
#define PCI_SUBCLASS_BRIDGE_PCMCIA              0x05
#define PCI_SUBCLASS_BRIDGE_NUBUS               0x06
#define PCI_SUBCLASS_BRIDGE_CARDBUS             0x07
#define PCI_SUBCLASS_BRIDGE_RACEWAY             0x08
#define PCI_SUBCLASS_BRIDGE_STPCI               0x09
#define PCI_SUBCLASS_BRIDGE_INFINIBAND          0x0a
#define PCI_SUBCLASS_BRIDGE_MISC                0x80

/* 0x07 communications subclasses */
#define PCI_SUBCLASS_COMMUNICATIONS_SERIAL      0x00
#define PCI_SUBCLASS_COMMUNICATIONS_PARALLEL    0x01
#define PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL    0x02
#define PCI_SUBCLASS_COMMUNICATIONS_MODEM       0x03
#define PCI_SUBCLASS_COMMUNICATIONS_GPIB        0x04
#define PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD   0x05
#define PCI_SUBCLASS_COMMUNICATIONS_MISC        0x80

/* 0x08 system subclasses */
#define PCI_SUBCLASS_SYSTEM_PIC                 0x00
#define PCI_SUBCLASS_SYSTEM_DMA                 0x01
#define PCI_SUBCLASS_SYSTEM_TIMER               0x02
#define PCI_SUBCLASS_SYSTEM_RTC                 0x03
#define PCI_SUBCLASS_SYSTEM_PCIHOTPLUG          0x04
#define PCI_SUBCLASS_SYSTEM_MISC                0x80

/* 0x09 input subclasses */
#define PCI_SUBCLASS_INPUT_KEYBOARD             0x00
#define PCI_SUBCLASS_INPUT_DIGITIZER            0x01
#define PCI_SUBCLASS_INPUT_MOUSE                0x02
#define PCI_SUBCLASS_INPUT_SCANNER              0x03
#define PCI_SUBCLASS_INPUT_GAMEPORT             0x04
#define PCI_SUBCLASS_INPUT_MISC                 0x80

/* 0x0a dock subclasses */
#define PCI_SUBCLASS_DOCK_GENERIC               0x00
#define PCI_SUBCLASS_DOCK_MISC                  0x80

/* 0x0b processor subclasses */
#define PCI_SUBCLASS_PROCESSOR_386              0x00
#define PCI_SUBCLASS_PROCESSOR_486              0x01
#define PCI_SUBCLASS_PROCESSOR_PENTIUM          0x02
#define PCI_SUBCLASS_PROCESSOR_ALPHA            0x10
#define PCI_SUBCLASS_PROCESSOR_POWERPC          0x20
#define PCI_SUBCLASS_PROCESSOR_MIPS             0x30
#define PCI_SUBCLASS_PROCESSOR_COPROC           0x40

/* 0x0c serial bus subclasses */
#define PCI_SUBCLASS_SERIALBUS_FIREWIRE         0x00
#define PCI_SUBCLASS_SERIALBUS_ACCESS           0x01
#define PCI_SUBCLASS_SERIALBUS_SSA              0x02
#define PCI_SUBCLASS_SERIALBUS_USB              0x03
#define PCI_SUBCLASS_SERIALBUS_FIBER            0x04    /* XXX _FIBRECHANNEL */
#define PCI_SUBCLASS_SERIALBUS_SMBUS            0x05
#define PCI_SUBCLASS_SERIALBUS_INFINIBAND       0x06
#define PCI_SUBCLASS_SERIALBUS_IPMI             0x07
#define PCI_SUBCLASS_SERIALBUS_SERCOS           0x08
#define PCI_SUBCLASS_SERIALBUS_CANBUS           0x09

/* 0x0d wireless subclasses */
#define PCI_SUBCLASS_WIRELESS_IRDA              0x00
#define PCI_SUBCLASS_WIRELESS_CONSUMERIR        0x01
#define PCI_SUBCLASS_WIRELESS_RF                0x10
#define PCI_SUBCLASS_WIRELESS_BLUETOOTH         0x11
#define PCI_SUBCLASS_WIRELESS_BROADBAND         0x12
#define PCI_SUBCLASS_WIRELESS_802_11A           0x20
#define PCI_SUBCLASS_WIRELESS_802_11B           0x21
#define PCI_SUBCLASS_WIRELESS_MISC              0x80

/* 0x0e I2O (Intelligent I/O) subclasses */
#define PCI_SUBCLASS_I2O_STANDARD               0x00

/* 0x0f satellite communication subclasses */
/*      PCI_SUBCLASS_SATCOM_???                 0x00    / * XXX ??? */
#define PCI_SUBCLASS_SATCOM_TV                  0x01
#define PCI_SUBCLASS_SATCOM_AUDIO               0x02
#define PCI_SUBCLASS_SATCOM_VOICE               0x03
#define PCI_SUBCLASS_SATCOM_DATA                0x04

/* 0x10 encryption/decryption subclasses */
#define PCI_SUBCLASS_CRYPTO_NETCOMP             0x00
#define PCI_SUBCLASS_CRYPTO_ENTERTAINMENT       0x10
#define PCI_SUBCLASS_CRYPTO_MISC                0x80

/* 0x11 data acquisition and signal processing subclasses */
#define PCI_SUBCLASS_DASP_DPIO                  0x00
#define PCI_SUBCLASS_DASP_TIMEFREQ              0x01
#define PCI_SUBCLASS_DASP_SYNC                  0x10
#define PCI_SUBCLASS_DASP_MGMT                  0x20
#define PCI_SUBCLASS_DASP_MISC                  0x80

/*
** PCI BIST/Header Type/Latency Timer/Cache Line Size Register.
*/
#define PCI_BHLC_REG                            0x0c

#define PCI_BIST_SHIFT                          24
#define PCI_BIST_MASK                           0xff
#define PCI_BIST(pci_bhlc_reg) \
            (((pci_bhlc_reg) >> PCI_BIST_SHIFT) & PCI_BIST_MASK)

#define PCI_HDRTYPE_SHIFT                       16
#define PCI_HDRTYPE_MASK                        0xff
#define PCI_HDRTYPE(pci_bhlc_reg) \
            (((pci_bhlc_reg) >> PCI_HDRTYPE_SHIFT) & PCI_HDRTYPE_MASK)

#define PCI_HDRTYPE_TYPE(pci_bhlc_reg) \
            (PCI_HDRTYPE(pci_bhlc_reg) & 0x7f)
#define PCI_HDRTYPE_MULTIFN(pci_bhlc_reg) \
            ((PCI_HDRTYPE(pci_bhlc_reg) & 0x80) != 0)

#define PCI_LATTIMER_SHIFT                      8
#define PCI_LATTIMER_MASK                       0xff
#define PCI_LATTIMER(pci_bhlc_reg) \
            (((pci_bhlc_reg) >> PCI_LATTIMER_SHIFT) & PCI_LATTIMER_MASK)

#define PCI_CACHELINE_SHIFT                     0
#define PCI_CACHELINE_MASK                      0xff
#define PCI_CACHELINE(pci_bhlc_reg) \
            (((pci_bhlc_reg) >> PCI_CACHELINE_SHIFT) & PCI_CACHELINE_MASK)

#define PCI_BHLC_CODE(bist,type,multi,latency,cacheline)                \
            ((((bist) & PCI_BIST_MASK) << PCI_BIST_SHIFT) |             \
             (((type) & PCI_HDRTYPE_MASK) << PCI_HDRTYPE_SHIFT) |       \
             (((multi)?0x80:0) << PCI_HDRTYPE_SHIFT) |                  \
             (((latency) & PCI_LATTIMER_MASK) << PCI_LATTIMER_SHIFT) |  \
             (((cacheline) & PCI_CACHELINE_MASK) << PCI_CACHELINE_SHIFT))

#define PCI_HDRTYPE_DEVICE                      0
#define PCI_HDRTYPE_PPB                         1
#define PCI_HDRTYPE_PCB                         2

/*
** Mapping registers
*/
#define PCI_MAPREG_START                        0x10
#define PCI_MAPREG_END                          0x28

#define PCI_MAPREG_ROM                          0x30
#define PCI_MAPREG_PPB_END                      0x18
#define PCI_MAPREG_PCB_END                      0x14

#define PCI_MAPREG_TYPE_MASK                    0x00000001
#define PCI_MAPREG_TYPE(pci_map_reg)            \
            ((pci_map_reg) & PCI_MAPREG_TYPE_MASK)

#define PCI_MAPREG_TYPE_MEM                     0x00000000
#define PCI_MAPREG_TYPE_IO                      0x00000001
#define PCI_MAPREG_ROM_ENABLE                   0x00000001

#define PCI_MAPREG_MEM_TYPE_MASK                0x00000006
#define PCI_MAPREG_MEM_TYPE(pci_map_reg)                        \
            ((pci_map_reg) & PCI_MAPREG_MEM_TYPE_MASK)

#define PCI_MAPREG_MEM_TYPE_32BIT               0x00000000
#define PCI_MAPREG_MEM_TYPE_32BIT_1M            0x00000002
#define PCI_MAPREG_MEM_TYPE_64BIT               0x00000004

#define PCI_MAPREG_MEM_PREFETCHABLE_MASK        0x00000008
#define PCI_MAPREG_MEM_PREFETCHABLE(pci_map_reg)                \
            (((pci_map_reg) & PCI_MAPREG_MEM_PREFETCHABLE_MASK) != 0)

#define PCI_MAPREG_MEM_ADDR(pci_map_reg)                        \
            ((pci_map_reg) & PCI_MAPREG_MEM_ADDR_MASK)
#define PCI_MAPREG_MEM_SIZE(pci_map_reg)                        \
            (PCI_MAPREG_MEM_ADDR(pci_map_reg) & -PCI_MAPREG_MEM_ADDR(pci_map_reg))
#define PCI_MAPREG_MEM_ADDR_MASK                0xfffffff0

#define PCI_MAPREG_MEM64_ADDR(pci_map_reg)                      \
            ((pci_map_reg) & PCI_MAPREG_MEM64_ADDR_MASK)
#define PCI_MAPREG_MEM64_SIZE(pci_map_reg)                              \
            (PCI_MAPREG_MEM64_ADDR(pci_map_reg) & -PCI_MAPREG_MEM64_ADDR(pci_map_reg))
#define PCI_MAPREG_MEM64_ADDR_MASK              0xfffffffffffffff0ULL

#define PCI_MAPREG_IO_ADDR(pci_map_reg)                                         \
            ((pci_map_reg) & PCI_MAPREG_IO_ADDR_MASK)
#define PCI_MAPREG_IO_SIZE(pci_map_reg)                                         \
            (PCI_MAPREG_IO_ADDR(pci_map_reg) & -PCI_MAPREG_IO_ADDR(pci_map_reg))
#define PCI_MAPREG_IO_ADDR_MASK                 0xfffffffc

#define PCI_MAPREG_SIZE_TO_MASK(size)                                   \
            (-(size))

#define PCI_MAPREG_NUM(offset)                                          \
            (((unsigned)(offset)-PCI_MAPREG_START)/4)

/*
** Cardbus CIS pointer (PCI rev. 2.1)
*/
#define PCI_CARDBUS_CIS_REG 0x28

/*
** Subsystem identification register; contains a vendor ID and a device ID.
** Types/macros for PCI_ID_REG apply.
** (PCI rev. 2.1)
*/
#define PCI_SUBSYS_ID_REG 0x2c

/*
** Interrupt Configuration Register; contains interrupt pin and line.
*/
#define PCI_INTERRUPT_REG               0x3c

typedef u_int8_t pci_intr_latency_t;
typedef u_int8_t pci_intr_grant_t;
typedef u_int8_t pci_intr_pin_t;
typedef u_int8_t pci_intr_line_t;

#define PCI_MAX_LAT_SHIFT                       24
#define PCI_MAX_LAT_MASK                        0xff
#define PCI_MAX_LAT(icr) \
            (((icr) >> PCI_MAX_LAT_SHIFT) & PCI_MAX_LAT_MASK)

#define PCI_MIN_GNT_SHIFT                       16
#define PCI_MIN_GNT_MASK                        0xff
#define PCI_MIN_GNT(icr) \
            (((icr) >> PCI_MIN_GNT_SHIFT) & PCI_MIN_GNT_MASK)

#define PCI_INTERRUPT_GRANT_SHIFT               24
#define PCI_INTERRUPT_GRANT_MASK                0xff
#define PCI_INTERRUPT_GRANT(icr) \
            (((icr) >> PCI_INTERRUPT_GRANT_SHIFT) & PCI_INTERRUPT_GRANT_MASK)

#define PCI_INTERRUPT_LATENCY_SHIFT             16
#define PCI_INTERRUPT_LATENCY_MASK              0xff
#define PCI_INTERRUPT_LATENCY(icr) \
            (((icr) >> PCI_INTERRUPT_LATENCY_SHIFT) & PCI_INTERRUPT_LATENCY_MASK)

#define PCI_INTERRUPT_PIN_SHIFT                 8
#define PCI_INTERRUPT_PIN_MASK                  0xff
#define PCI_INTERRUPT_PIN(icr) \
            (((icr) >> PCI_INTERRUPT_PIN_SHIFT) & PCI_INTERRUPT_PIN_MASK)

#define PCI_INTERRUPT_LINE_SHIFT                0
#define PCI_INTERRUPT_LINE_MASK                 0xff
#define PCI_INTERRUPT_LINE(icr) \
            (((icr) >> PCI_INTERRUPT_LINE_SHIFT) & PCI_INTERRUPT_LINE_MASK)

#define PCI_INTERRUPT_CODE(lat,gnt,pin,line)            \
          ((((lat)&PCI_INTERRUPT_LATENCY_MASK)<<PCI_INTERRUPT_LATENCY_SHIFT)| \
           (((gnt)&PCI_INTERRUPT_GRANT_MASK)  <<PCI_INTERRUPT_GRANT_SHIFT)  | \
           (((pin)&PCI_INTERRUPT_PIN_MASK)    <<PCI_INTERRUPT_PIN_SHIFT)    | \
           (((line)&PCI_INTERRUPT_LINE_MASK)  <<PCI_INTERRUPT_LINE_SHIFT))

#define PCI_INTERRUPT_PIN_NONE                  0x00
#define PCI_INTERRUPT_PIN_A                     0x01
#define PCI_INTERRUPT_PIN_B                     0x02
#define PCI_INTERRUPT_PIN_C                     0x03
#define PCI_INTERRUPT_PIN_D                     0x04
#define PCI_INTERRUPT_PIN_MAX                   0x04

#endif /* ! PCIREG_H_ */

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